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Professor Asenov, the founder and CEO of Semiwise is the world leader in simulation of statistical CMOS variability. He has more than 800 publications in this and related fields available at Google scholar, with more than 11,400 citations, h-index of 47 and i10-index of 217.


Asenov published the first comprehensive ‘atomistic’ simulation study of statistical variability introduced by random discrete dopants “Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 micro-meter MOSFET's: A 3-D" atomistic" simulation study” (1998) with more than 680 citations.


In an invited review paper “Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs” (2003) with more than 590 citations he showed that the statistical variability increases rapidly with the increase of the doping N in the channel of the transistor as N^0.4.


In the paper “Suppression of random dopant-induced threshold voltage fluctuations in sub-0.1-micro-meter MOSFET's with epitaxial and delta-doped channels” (1999) with more than 200 citations he has shown the way of designing variability resistant transistors adopted by companies like Suvolta and Atomera.


The accuracy of the ‘atomistic simulator GARAND developed under the supervision of Asenov has been demonstrated at 45nm Bulk CMOS in “Quantitative evaluation of statistical variability sources in a 45-nm technological node LP N-MOSFET”, at 32 nm bulk CMOS in “Simulation Study of Dominant Statistical Variability Sources in 32-nm High-K Metal Gate CMOS” and at 22 nm FinFET CMOS in “Accurate simulation of transistor-level variability for the purposes of TCAD-based device-technology co-optimization”.


Professor Asenov has engineered the development of the TCAD based Variability Aware Design Technology Co-Optimisation (DTCO) described in “Variability aware simulation based design-technology cooptimization (DTCO) flow in 14 nm FinFET/SRAM cooptimization”, widely adopted now by leading semiconductor manufacturers.