Semiwise offers CMOS technology and transistor design IP developed using the leading atomistic and statistical advanced device simulator GARAND (now proprietary to Synopsys Inc.) that reduces the statistical variability in transistors, and therefore:


  • Reduces significantly the stand-by leakage and increases battery life in Internet of Things (IoT) applications. This is fully quantified through simulations with advanced statistical and atomistic software. 

  • Allows very low supply voltage design including near threshold and subthreshold design, which reduces the active power and further increases IoT battery life. This is fully quantified via the GSS (now proprietary to Synopsys Inc.) Design–Technology-Co-Optimisation simulation flow (DTCO). 


Application of Semiwise IP will result in a significant improvements in the performance and the reliability of circuits in IoT applications.  


The Semiwise IP covers conventional (bulk) CMOS technology, Fully Depleted SOI (FDSOI) technology and FinFET CMOS technology. The bulk CMOS IP is applicable down to 20 nm and 28 nm technologies. It will work with all previous generations including 40 nm or larger CMOS technologies.

© 2017-2018 Semiwise Ltd.